IcarusVerilog

Icarus Verilog is intended to compile ALL of the Verilog HDL, as described in the IEEE-1364 standard. Of course, it's not quite there yet. It does currently handle a mix of structural and behavioural constructs.

homepage: https://steveicarus.github.io/iverilog/

version	toolchain
12.0	GCCcore/13.3.0

(quick links: (all) - 0 - a - b - c - d - e - f - g - h - i - j - k - l - m - n - o - p - q - r - s - t - u - v - w - x - y - z)